Job Description

We are seeking a Senior ASIC Engineer specializing in Static Timing Analysis (STA) to join our team. In this role, you will be responsible for developing and validating timing constraints, ensuring RTL quality, and driving timing closure for complex ASIC designs.

Key Responsibilities

• Develop and validate multi-mode/multi-corner timing constraints (SDC) for RTL and signoff.
• Perform pre-route timing checks and Quality-of-Results (QoR) cleanup for STA handoff.
• Utilize Tcl scripting (EDA tools + Linux) to automate timing checks and improve efficiency.
• Analyze timing reports (Synopsys Primetime/Design Compiler) to identify and resolve design/constraint issues.
• Collaborate with cross-functional teams to achieve timing closure in complex, hierarchical designs.
• Drive process improvements to enhance RTL quality and early-stage issue detection.

Qualifications

• 6+ years of experience in ASIC timing analysis (STA/SDC constraints).
• Proficiency with EDA tools (e.g., Synopsys PT/DC, Spyglass, Fishtail).
• Strong Tcl/Python scripting skills for automation.
• Bachelor’s degree in Electrical/Computer Engineering or related field.
• Excellent problem-solving and communication skills.

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